The present invention concerns the adaptation of a processor which does not natively support co-processing into a co-processing system.
In many processing applications, co-processors are utilized to supplement a primary processor. Co-processors can be of particular advantage when a primary processor is either too special purpose or too general purpose to efficiently perform some tasks required in a processor application.
Generally, in applications in which co-processors are used, the co-processor has a very tightly coupled interface with the primary processor. This interface is preferably at the level of the hardware cycle of the primary processor and the co-processor. The tight coupling of such an interface makes for very efficient co-operation between the processors. Alternately, the primary processor can be more loosely coupled to the co-processor using, for example, processor interrupts or polling sequences to synchronize the operation of the co-processor with the primary processor.
While co-processing can be advantageous in many circumstances, unfortunately, not all primary processors natively support co-processing. For example, a 53C710 SCSI I/O processor available from NCR Corporation, having a business address at 1635 Aeroplaza Dr., Colorado Springs, Colo. 80916, may be used in an input/output (I/O) device which interfaces an Extended Industry Standard Architecture (EISA) I/O bus to a SCSI port. The EISA Specification is available from BCPR Services, Inc. which has a business address of 1400 L Street NW., Washington, D.C. 20005. While the NCR 53C710 SCSI I/O processor is adapted to interface with information communicated over a SCSI port, it does not natively support a co-processor. Nevertheless such a co-processor is desirable in order to efficiently perform direct memory access (DMA) transactions using master bus transactions over an EISA I/O bus.